For high speed performance, CMOS circuit designers often implement various functions using "dynamic logic," that is, logic that includes circuit nodes which are not always held to the supply voltage VDD (high) or ground VSS (low). The nodes are alternatively "precharged," to drive them each to a predetermined state, for example, to a high state, and then evaluated under the control of an evaluation signal that is, in turn, controlled by a system clock. During the evaluation period, that is, when the evaluation signal is, for example, high, one of these nodes may change state, in this example, discharge to a low state, in response to the current state of one or more input signals that are associated with the nodes. For convenience, these nodes are hereinafter referred to as "dynamic nodes."
Often the evaluated state of the dynamic nodes must be captured by a latch, before the results are passed on to receiving circuitry. For high-speed applications, the latch must be able to capture the evaluated state relatively quickly. Otherwise, the circuits that utilize the evaluated information will in turn be delayed. This may result in a slow down of the entire system if the latch is part of a critical signal path.
There are generally two constraints to the design of the latch, namely, the area, or "chip real estate," the latch may consume and the available power. Known prior latch designs that satisfy stringent area and/or power constraints are relatively slow. For example, cross-coupled NAND gate latches have slow-falling output delays. A known prior dual cross-coupled NAND gate latch operates relatively quickly, but requires properly timed input signals for fast operation. Further, the latch requires additional logic, which increases both the area and the power consumed by the latch.